Conventional testing of integrated circuits (ICs) is expensive and time consuming. Scan testing is no longer considered a feasible approach for cost sensitive testing. In particular, scan testing requires too much time and tester memory. Conventional solutions to cost sensitive testing include using functional test patterns. However, such test patterns are inefficient and often complicated.
With large designs, the scan test approach has several functional limitations. Such limitations include (i) lack of real-time testing and (ii) increased test time as designs increase in size. In particular, to test a device with 30,000 flip-flops (FFs), an automatic test pattern generation (ATPG) tool can generate 1,200 vectors. This results in 36,000,000 clock cycles to test the respective device and a test time of 1,800 ms using a 20 MHz clock. Such an approach also uses a large amount of tester memory.
Conventional built in self test (BIST) approaches have been set up such that some of the registers in the design are configured as pattern generators and other registers are configured to perform cyclical redundancy checks (CRCs). However, such an approach will not work if there is a direct feedback path to the source register. In particular, in conventional BIST approaches the same register cannot be simultaneously configured as a generator and as a CRC.
It would be desirable to implement a test strategy using a built in self test (BIST) rather than scan testing where each of a number of flip-flops is simultaneously implemented as generator and as a CRC.